Session A5 - Molecular Electronics: Challenges for Computing and Sensing.
INVITED session, Monday morning, March 22
524AB, Palais des Congres
Several alternatives have been proposed to go beyond CMOS technology. At NASA Ames Center for Nanotechnology (NACNT), we have focused on building vertically aligned semiconductor single crystal nanowire (NW) and molecular wire (MW) platforms for 3D integration of nanoelectronic devices and systems. The platforms allow high performance device architecture implementation, for example, vertical surround gate transistors (VSGT) and VSGT based memory and logic and multilevels or multibits information processing, which are radically different from conventional planar CMOS architectures. This approach allows ultrahigh density fabrication and integration while compatible with typical CMOS processing. In this talk, we will present recent demonstrations of multilevel MW-NW memory devices and vertical top and surround gate NW transistors. In addition to intriguing chemistry and physics, the demonstrations also reveal challenges in materials, interfaces, integration, and heat dispassion. However, given the flexibility in materials choice, nanoscale interface, 3D integration and compatibility with CMOS fabrication and operation, these challenges can be turned into opportunities to go beyond CMOS limit. Contributions from Jie Han, H.T.Ng and Bin Yu are acknowledged.